Enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration
نویسندگان
چکیده
منابع مشابه
2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process
With the consideration of low standby leakage in nanoscale CMOS processes, a new 2×VDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCRbased) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage...
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polysilicon diodes to trigger ESD protection device is proposed to achieve excellent on-chip ESD protection. Design methodology of this novel ESD clamp circuit has been derived in detail. Some controlled factors in the novel ESD clamp circuit can be exactly calculated to design a suitable ESD clamp circuit for different power supply applications. By adding this efficient power-rail ESD clamp ci...
متن کاملDesign of 2×VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
A low-leakage 2×VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit composed of the siliconcontrolled rectifier (SCR) device and new ESD detection circuit, realized with only thin-oxide 1× VDD devices, has been proposed with consideration of gate leakage current. By reducing the voltage across the gate oxides of the devices in the ESD detection circuit, the whole power-rail ESD ...
متن کاملESD Detection Circuit controlling to using ESD Clamp Circuit with adjustable holding voltage and PMOS-Based Power
A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65nm 1.2V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much ...
متن کاملSubstrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits
New electrostatic discharge (ESD) clamp devices for using in power-rail ESD clamp circuits with the substratetriggered technique are proposed to improve ESD level in a limited silicon area. The parasitic n–p–n and p–n–p bipolar junction transistors (BJTs) in the CMOS devices are used to form the substrate-triggered devices for ESD protection. Four substrate-triggered devices are proposed and in...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2017
ISSN: 1349-2543
DOI: 10.1587/elex.14.20160901